Random access memory (RAM) devices containing ferroelectric regions therein that can be polarized to provide nonvolatile data storage are typically referred to a ferroelectric random access memory (FRAM) devices. FRAM devices possess certain unique advantages over many conventional memory devices because they typically have high read/write operating speed, retain data in a nonvolatile state and have high reliability and durability. One such FRAM device having ferroelectric transistor (FT) unit cells therein is disclosed in U.S. Pat. No. 5,412,596 to Hoshiba, entitled Semiconductor Storage Device With A Ferroelectric Transistor Storage Cell. However, to prevent inadvertent read operations when a FT is programmed into a normally-on state, a switching transistor (ST) is also provided in each unit cell, in series with each FT. Unfortunately, the addition of a switching transistor to prevent inadvertent read operations increases the unit cell size and reduces the integration density of the memory device. To address this problem, U.S. Pat. No. 5,541,871 to Nishimura et al. entitled Nonvolatile Ferroelectric-Semiconductor Memory, discloses a single ferroelectric transistor unit cell having a control gate (CG) and a memory gate (MG) disposed opposite a channel region 26.
Notwithstanding these attempts to develop improved FRAM devices, there continues to be a need for improved memory devices which are reliable, can be read nondestructively and have reduced unit cell size.